The present invention generally relates to integrated circuits having multiple power domains, and, more particularly, to a system for isolating power domains of an integrated circuit.
Integrated circuits (ICs) integrate various digital as well as analog circuits (hereinafter referred to as “functional blocks”) on a single chip for performing various operations. The functional blocks include a large number of transistors. With advancements in semiconductor technology, the number of transistors is increasing continually, which results in increased power consumption.
Power consumption is a major concern, especially for handheld devices such as mobile phones, smart phones, laptops, cameras, personal digital assistants (PDAs), and tablets that are constrained due to limited energy available from batteries. Further, increases in the power consumption result in increases in the heat generated by the IC, which can adversely affect performance.
A known technique to reduce power consumption in an IC is to include one or more power management units, also referred to as power gating controllers, and define multiple power domains. An IC with multiple power domains also may be able to support several customer use-cases in which one or more power domains can be powered down on an as-needed basis. The IC also may be operable in multiple power modes, viz., high and low power modes. The high power mode is referred to as a high performance mode. A power domain that can be powered down when the functionality provided by the power domain is not required is referred to as a power-off domain. Generally, power domains that have high power consumption are power-off domains. Such power domains are operational when the IC is in the high power mode and powered down when the IC is in the low power mode. A power domain that is always powered up is referred to as a power-on domain. Generally, power domains that have low power consumption and perform essential functions are power-on domains. Such power domains are always operational, i.e., both when the IC is in high power mode and in the low power mode.
A power gating controller manages the power consumption of the IC by powering up and powering down the power domains of the IC based on a power mode. Each power domain includes one or more functional blocks. The IC includes different power supply rails for the power domains. The power supply rails provide voltages to the functional blocks of the power domains that are necessary for their operation. Switches such as such as bipolar junction transistors (BJTs) and metal-oxide semiconductor field effect transistors (MOSFETs) may be used to connect the high power supply rails to the functional blocks.
Power consumption is reduced by powering down one or more power domains when the functionality provided by those power domains is not required. The power gating controller provides power-down signals to the switches connecting the voltage rails to the functional blocks. The power-down signals are indicative of powering up or powering down corresponding power domains. For example, a switch is opened when the power gating controller wants to power down a corresponding power domain and the switch is closed when the power gating controller wants to power-up the domain.
However, when a power domain is powered down, an output signal from the power domain may be at neither logic high nor logic low such that another power domain that receives the signal may enter an unknown state, which may impair the operation of the IC.
One technique to overcome the aforementioned problem is to isolate a power domain that is connected to another power domain. FIG. 1 is a schematic block diagram of a conventional IC 100 that includes a power gating controller 102, a first power domain 104, an OR gate 106, a NOT gate 108, an AND gate 110, a latch 112, and a second power domain 114. The IC 100 is operable in low and high power modes.
The power gating controller 102 generates isolation enable, reset, and power-down signals (VISO_EN, VR, and VPD, respectively). The isolation enable signal (VISO_EN) is for isolating the second power domain 114 from the first power domain 104. The power gating controller 102 controls the power consumption of the IC 100 by controlling the isolation enable, reset, and power-down signals (VISO_EN, VR, and VPD, respectively).
For example, the first power domain 104 can be powered down by the power gating controller 102 when the functionality provided by the first power domain 104 is not required. Thus, the first power domain 104 is operational when the IC 100 is in the high power mode and is powered down when the IC 100 is in the low power mode. The first power domain 104 is connected to the power gating controller 102 for receiving the reset and power-down signals (VR and VPD). The first power domain 104 outputs first, second, and third output signals (VOUT_1, VOUT_2, and VOUT_3, respectively). The first, second, and third output signals (VOUT_1, VOUT_2, and VOUT_3) may be data signals, control signals, reset signals, handshaking signals, bit signals, etc. The first power domain 104 includes a first set of functional blocks (not shown) connected between first high and first low power supply rails (not shown). The IC 100 further includes a switch (not shown) that connects the first high power supply rail to the first set of functional blocks, i.e., the first power domain 104. The power gating controller 102 provides the power-down signal (VPD) to the switch. The switch is opened when the power gating controller 102 enables the power-down signal (VPD), thereby powering down the first power domain 104. The switch is closed when the power gating controller 102 disables the power-down signal (VPD), thereby powering up the first power domain 104.
The OR gate 106 has first and second input terminals connected to the first power domain 104 and the power gating controller 102 for receiving the first output and isolation enable signals (VOUT_1 and VISO_EN) and generates a first isolation signal (VISO_1).
The AND gate 110 has a first input terminal connected to the first power domain 104 for receiving the second output signal (VOUT_2) and a second input terminal for receiving an inverted isolation enable signal (VINV_ISO_EN) from the NOT gate 108, and outputs a second isolation signal (VISO_2).
The latch 112 has an input terminal connected to the first power domain 104 for receiving the third output signal (VOUT_3) and an enable terminal for receiving the inverted isolation enable signal (VINV_ISO_EN). The latch 112 outputs the third isolation signal (VISO_3). The latch 112 is disabled when the isolation enable signal (VISO_EN) is enabled. Thus, the latch 112 retains a sampled value of the third output signal (VOUT_3) when the isolation enable signal (VISO_EN) is active. For a signal provided by the first power domain 104 to the second power domain 114, one of the OR gate 106, the AND gate 110, and the latch 112 is used to isolate the second power domain 114 from the first power domain 104.
The second power domain 114 is connected to the OR gate 106, the AND gate 110, and the latch 112 for receiving the first, second, and third isolation signals (VISO_1, VISO_2, and VISO_3). The second power domain 114 includes a second set of functional blocks (not shown) connected between second high and second low power supply rails (not shown) that are required for the operation of the second set of functional blocks.
When the power gating controller 102 determines that the second power domain 114 is to be isolated from the first power domain 104, the power gating controller 102 enables the reset signal (VR). Elements such as flip-flops and latches of the first power domain 104 enter a pre-determined state when the reset signal (VR) is active. Thus, the first, second, and third output signals (VOUT_1, VOUT_2, and VOUT_3) enter a pre-determined state. Subsequently, the power gating controller 102 enables the isolation enable signal (VISO_EN), which in this example is high active.
The OR gate 106 receives the isolation enable signal (VISO_EN) and generates the first isolation signal (VISO_1) at logic high state irrespective of the logic state of the first output signal (VOUT_1). The AND gate 110 receives the inverted isolation enable signal (VINV_ISO_EN) at logic low state and generates the second isolation signal (VISO_2) at logic low state irrespective of the logic state of the second output signal (VOUT_2). The latch 112 receives the inverted isolation enable signal (VINV_ISO_EN) at logic low state and hence, is disabled. Thus, the latch 112 holds a sampled value of the third output signal (VOUT_3), so the third isolation signal (VISO_3) is the latched third output signal (VOUT_3).
The second power domain 114 receives the first, second, and third isolation signals (VISO_1, VISO_2, and VISO_3) at fixed logic states when the isolation enable signal (VISO_EN) is active, so any changes in the first, second, and third output signals (VOUT_1, VOUT_2, and VOUT_3) do not affect the logic state of the first, second, and third isolation signals (VISO_1, VISO_2, and VISO_3) and hence, the second power domain 114 is isolated from the first power domain 104. Thus, the OR gate 106, the AND gate 110, and the latch 112 isolate the second power domain 114 from the first power domain 104. The OR gate 106, the AND gate 110, and the latch 112 are also referred to as isolation circuits 106, 110, and 112, respectively.
After enabling the isolation enable signal (VISO_EN), the power gating controller 102 enables and provides the power-down signal (VPD) to the switch connecting the first high power supply rail to the first set of functional blocks, thereby opening the switch. Thus, the first power domain 104 is powered down.
When the power gating controller 102 determines that the first power domain 104 is to be powered up, the power gating controller 102 disables the power-down signal (VPD), which closes the switch. Subsequently, the power gating controller 102 disables the isolation enable signal (VISO_EN). After disabling the isolation enable signal (VISO_EN), the power gating controller 102 disables the reset signal (VR). Thus, the power gating controller 102 disables the power-down, isolation enable, and the reset signals (VPD, VISO_EN, and VR, respectively) to powering up the first power domain 104.
However, when the power gating controller 102 enables the isolation enable signal (VISO_EN), the OR gate 106, the AND gate 110, and the latch 112 generate the first, second, and third isolation signals (VISO_1, VISO_2, and VISO_3, respectively). Therefore, it is not possible to change the logic state of the first, second, and third isolation signals as per requirement, after the IC 100 has been manufactured. Further, an IC design corresponding to the IC 100 is simulated to ensure that the correct isolation circuit is selected for each signal provided by the first power domain 104 to the second power domain 114, thereby is very time consuming. Also, there is a possibility of the wrong isolation circuits being selected. As a result, the operation of second power domain 114 may be hampered when the IC 100 is in the low power mode.
Therefore, it would be advantageous to have an isolation circuit that isolates a power domain from another power domain and enables selection of different configurations of the isolation circuit post-manufacturing.